1. Field of the Invention
This disclosure relates to a method of forming a semiconductor device, and more particularly, to a method of forming a fin field effect transistor (finFET) by using a damascene method.
2. Description of the Related Art
Metal-oxide-semiconductor field effect transistor (MOSFET) is gradually miniaturized for high performance and high integration. To enhance the integration degree of device a new technique has been proposed continuously and this brings about a production of prominent devices from the viewpoint of operation or size.
As one technique to enhance the integration degree of device, a fin field effect transistor was proposed. Such a transistor is formed by a vertical structure of body region, and the name is derived from a similarity to a fish's dorsal fin.
The finFET has a powerful advantage in that much more current can be controlled without increasing the size of device. However, one disadvantage is that it is difficult to electrically isolate individual finFETs. To solve the disadvantages of finFETs, the finFET has been conventionally manufactured from an SOI (Silicon-On-Insulator) substrate. Particularly, fins of the transistor have been formed from a silicon layer provided on an upper part of buried oxide (BOX) layer. Thus, respective fins have an electrically isolated structure by the buried oxide layer existing under the fins.
However, forming the finFET from the SOI substrate is not ideal either. The cost of the SOI substrate is remarkably high as compared with a bulk substrate and the SOI substrate is not compatible with other existing manufacturing process techniques.
Thus, methods for developing finFETs from a bulk substrate have been proposed, and this has advantage of a high compatibility with existing flat type semiconductor techniques.
One example of a conventional technique for a method of forming the fin FET on a bulk substrate is found in U.S. Pat. No. 6,642,090 to Fried et al.
Another example of a conventional technique for forming a finFET from a bulk substrate is disclosed in the article “A 40 nm body-tied FinFET(OMEGA MOSFET) using bulk Si wafer”, which was announced in the Fourth International Symposium on Nanostructures and Mesoscopic Systems held on Feb. 17 through Feb. 21, 2003, in U.S.A, under the title for the collection of learned papers as “Low-dimensional Systems and Nanostructures”, by a writer of Elsevier B. V. in the collection of learned papers as ‘Physica E, Volume 19, Issues 1–2, Pages 6–12 (July 2003)’.
The conventional techniques provide a method of forming the finFET on the bulk substrate, but do not provide a method of overcoming a side effect caused in forming an upper edge portion of the fin in a sharpened shape. Furthermore, in forming a gate electrode, an etching process is performed entirely for a device isolation film surrounding the fin so as to expose a predetermined portion of active region having a shape of the fin, and then a conductive layer is deposited. Subsequently, the conductive layer is etched by a predetermined pattern to form a gate electrode. In forming the gate electrode, an absolute etching amount increases, and furthermore, causes a short between the formed gate electrodes. There also is a problem that an etching byproduct forms a space in the gate electrode by the increase of etching amount. After forming the gate electrode, an insulation layer is formed in a device isolation region, thus the process is complicated.
Embodiments of the invention address these and other disadvantages of the conventional art.